The present invention generally relates to communications systems and, more particularly, to a receiver.
In the ATSC (Advanced Television Systems Committee) standard for digital terrestrial television (DTV) in the United States (e.g., see, United States Advanced Television Systems Committee, “ATSC Digital Television Standard”, Document A/53, Sep. 16, 1995), the modulation system consists of a suppressed carrier vestigial sideband (VSB) modulation with an added small in-phase pilot at the suppressed carrier frequency, 11.3 dB below the average signal power, at the lower VSB signal edge. An illustrative spectrum for an ATSC VSB signal is shown in FIG. 1.
In a communications receiver, such as an ATSC receiver, it may be difficult or impossible to perform continuous “blind” timing (sampling clock) recovery, i.e., recovery which is not making use of the knowledge of the bit stream being received. In such instances, data-aided recovery may be implemented to supplement the “blind” methods. Data-aided timing recovery uses a decoded (or training) bit stream in conjunction with the received modulated stream to generate sampling error information to drive a Symbol Timing Recovery (STR) Loop.
For example, in an ATSC receiver an estimate of the transmitted bit stream is available at the equalizer output, while the system interpolator (used to adjust the timing phase) is usually located before the equalizer. However, this arrangement creates a problem when the equalizer is located inside the STR loop because it creates unwanted interaction between the two. As such, another way to perform data-aided recovery is for the equalizer to assume the function of tracking the residual timing frequency and/or phase offset (provided the offset is slow enough for the equalizer to track). Unfortunately, the problem with this method is that as the main equalizer tap changes to correct for the sampling drift, the sampling drift may exceed the equalizer range. This is conceptually illustrated in FIG. 2. For the purposes of describing the problem an equalizer 50 comprises a feed-forward filter having a shift register 51. Associated with each sample is a tap (not shown) of the feed-forward filter. The shift register 51 stores N samples of an input signal 49 at sample times provided by a sample clock (not shown). At a time T1, the main tap of equalizer 50 is associated with the sample at shifter register location 52. However, sampling drift occurs over time in the direction of arrow 53 such that at a subsequent time, T2, the main tap of equalizer 50 is adjusted to be associated with the sample at shift register location 54 to correct for this sample drift. Unfortunately, as the sampling drift continues over time, as represented by arrow 55, the main tap of equalizer 50 can no longer be adjusted to correct for the sampling drift, since the main tap would have to be associated with the sample located at shift register location 56—as represented in dotted line form, which exceeds the range of the equalizer since only N taps are available. A common way to solve this problem is to prevent the equalizer taps from consistently drifting in either direction by having the time-base locked by other means (blind or data-aided). However, even this solution does not prevent exceeding the range of the equalizer because of changes in the transmission channel response.